A CMOS Binary Adder Using a Quaternary Ganged-Logic Internal Node
نویسندگان
چکیده
This paper describes the design of a novel CMOS binary fulladder structure which incorporates four-valued signalling internally. A biased CMOS pseudo-lineaadder provides a quaternary signal representing the number of ones in the three binary inputs. Three area-ratioed CMOS inverters interpret this to provide three binary signals which, combined in conventional static CMOS logic, generate the sum and carry outputs. The resulting "Ganged-Logic Adder" (GLA) is competitive in situations where higher static power dissipation and reduced intemal noise margins can be tolerated in exchange for much lower input capacitance and faster carry propagation.
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